Digital dividers are a common building block in many different kinds of electronic systems. Frequency generators often use dividers to reduce an input frequency to a desired frequency. Phase-locked loops (PLL's) use a divider in the feedback path to multiply the clock frequency. PLL's with a divider on the input as well as a feedback-path divider can be used to generate arbitrary-frequency clocks. The output frequency is the ratio of the terminal counts for the two dividers.
Digital dividers are commonly implemented as counters that output a pulse after a predetermined number of input clock pulses have been received. These simple dividers count a whole number (M) of pulses. Additional logic may be used to reset the counter after half of a clock pulse once the terminal count M has been reached, thus achieving division by M.5, a simple fractional, non-whole number.
Such dividers are not able to divide by an arbitrary fraction, such as M.N, where M is the integer part and N is the fractional part of a real number. Arbitrary fractional divisors such as 5.3, 8.2, and 3.7 are difficult to implement.
Other dividers switch between a count of M and a count of M+1. Over a long time, the average frequency is determined by the ratio of the time the count is M or M+1. However, jitter is introduced since the instantaneous frequency is determined by either M or M+1.
Logic circuits have been used to divide by a fraction rather than a whole number. See for example U.S. Pat. No. 5,287,296 by Bays et al., and assigned to AT&T. Simple logic circuits often produce uneven clock periods which are undesirable. More complex logic circuits such as adders/accumulators have been used for fractional dividers. See for example, U.S. Pat. Nos. 4,494,243, 4,241,408, 5,088,057, and 5,235,531. These complex adders are expensive in die area and can increase latency or limit the frequency of the generated clock. Overflow may be a problem with complex adders.
Dividers are often used in PLL's. More recently, PLL's that slowly change the frequency over time are being used to reduce electromagnetic interference (EMI). See for example, "EMI Reduction for a Flat-Panel Display Controller Using Horizontal-Line-Based Spread Spectrum", U.S. Pat. No. 5,757,338, U.S. Ser. No. 08/701,814, also assigned to NeoMagic Corp. of Santa Clara, Calif. It is desired to improve the stability of such modulated PLL's and improve the smoothness of the generated clock.
What is desired is a fractional divider with a low-jitter output. Precise division is desirable using relatively simple circuits. Small counter divisors rather than large divisors are desirable when the fractional divider is used in a PLL. Smooth frequency transitions over time, such as for clock modulation, is desirable.